1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method of forming a storage node of capacitor in a semiconductor memory such as a DRAM (Dynamic Random Access Memory) and a structure thereof.
2. Description of the Related Art
A memory cell of DRAM is generally constructed of one access transistor and one storage capacitor. The capacitor is largely classified as a laminated type or a trench type depending on its formed position on a semiconductor substrate.
Semiconductor manufacturers for manufacturing a semiconductor memory that employs the laminated-type capacitor have continuously researched producing capacitors with a higher capacitance in a limited area in conformity with various requirements of semiconductor users. The need for this continuous research is derived from the high integration of memory cells that produces a tightened critical dimension which results in low capacitance of the memory cells. However, in order to guarantee a refresh operating period within a range of regulated value, the capacitance must instead be increased.
Capacitors are generally composed of a storage node as a lower electrode node and a plate node as an upper electrode. High integration causes the bottom critical dimension (CD) of the storage node to be too small which causes a leaning phenomenon resulting in the collapse of the storage node.
To prevent the leaning phenomenon, two methods have widely been used in this field. First is the method of increasing the bottom CD of straight type storage node. Second is the a method of lowering the height of storage node. However, the straight type method is undesirable because it is difficult to increase the bottom CD after a design rule was first decided, and the latter method is undesirable because it is unlikely to obtain the desired capacitance.
The former method was recently improved to provide a larger bottom CD and reduce the occurrence rate of the leaning phenomenon within a limited area. In this improved method, and in forming the storage node of the capacitor, an active region, a gate, a bit line contact, a storage node contact or buried contact, and bit line patterns are formed in a diagonal direction slightly slanted as compared with the existing straight structure, and thereon, the capacitor storage node is formed. This improved method significantly increases the bottom CD of the storage node as compared with the storage node of the existing straight type, and this is known in this field as a diagonal structure. However, this diagonal structure has severely complicated manufacturing processes in forming the storage node.
To avoid the complicated manufacturing processes of the diagonal structure, a new method for forming a storage node of square type was recently developed which shared advantages of the straight structure and the diagonal structure. In this method for the square type, an active region, a gate, a bit line and a capacitor storage node contact etc. are formed by the existing straight structure. Then, entirely thereon, a buffer layer is formed, and a contact is formed in the buffer layer, to thus connect the capacitor storage node of square type with a capacitor storage node contact of the straight structure. This new method has been regarded as increasing the storage node of the square type so that the bottom CD of the capacitor storage node is largely increased to about twice that of the storage node of the straight type based on the straight structure.
The method of manufacturing the storage node of square type in the prior art will be described referring to FIGS. 1 through 6, as follows, only to provide a thorough understanding of the present invention to be described later.
FIG. 1 is a plan view illustrating a disposed relationship for storage nodes of capacitor based on a square type in a semiconductor memory according to an example of the prior art. FIGS. 2 to 6 are sectional views showing sequential processes in manufacturing the storage node referred to FIG. 1.
Referring first to FIG. 1, vertically on the drawing, six word line patterns 13 as gates of a plurality of access transistors are formed, and horizontally on the drawing, four bit line patterns 16 connected to drains of the access transistors are formed. Storage nodes 23 of square type of the capacitors form an oblong structure in a diagonal direction to the bit line patterns 16 and the word line patterns 13. Herewith, each contact 17 of the storage node of capacitor and its lower structure are formed by a straight structure as the afore-mentioned. A reference number 14 indicates a bit line contact for connecting a bit line with a drain, and 14a designates a bit line pad. FIGS. 2 to 6 are sectional views taken along A–A′ and B–B′ cutting lines shown in FIG. 1.
On the left drawings of FIGS. 2 through 6, cross-sectional views taken along A–A′ cutting line direction of FIG. 1, namely, the direction of a word line connected to a gate of access transistor, are illustrated per process. On the right drawings of FIGS. 2 to 6, cross-sectional views taken along B–B′ cutting line direction of FIG. 1, namely, the direction of a bit line connected to a drain of the access transistor, are illustrated per process.
FIG. 2 illustrates a structure before forming a storage node of capacitor having a square type in a DRAM based on a capacitor over bitline (COB) structure. A device separate layer 3 is formed on a determined region of a semiconductor substrate 11 to define a plurality of active regions. A gate oxide layer 5 is formed on the active regions. Thereon, a plurality of parallel word line patterns 13 traversing the active regions are formed. The word line pattern 13 contains a word line 7b and a capping layer pattern 7c laminated sequentially. An impurity ion is implanted into the active regions by using the word line pattern 13 and the device separate layer 3 as an ion implantation mask, to form impurity regions 4s, 4d. The active impurity regions 4d between one pair of word line patterns 13 traversing the respective active regions are pertinent to a common drain region of a DRAM cell transistor. Further, the impurity region 4s formed on both sides of each common drain region 4d is pertinent to a source region of the DRAM cell transistor. A word line spacer 7a is formed on a sidewall of the gate oxide layer 5 and the word line patterns 13. A first interlayer insulation layer 13a is formed on an entire face of the semiconductor substrate containing the word line spacer 7a. The first interlayer insulation layer 13a is etched by using an etch mask pattern, to form the bit line pad 14a connected with the common drain region 4d and a capacitor storage node pad 12 connected with the source region 4s. Then, a second interlayer insulation layer 16a is formed on an entire face of the semiconductor substrate containing the bit line pad 14a and the capacitor storage node pad 12. The second interlayer insulation layer 16a is patterned to form the bit line contact 14 referred to FIG. 1. Then, the bitline contact 14 is connected with the plurality of bit line patterns 16 having a sidewall spacer 15. The bit line patterns 16 are formed, involving a bit line 16b and a bit line capping layer pattern 16c each laminated sequentially and traversing the word line patterns 13. Each bit line 16b is electrically connected to the bit line pad 14a through the bit line contact 14. A third interlayer insulation layer 15a is formed on an entire face of the semiconductor substrate containing the bit line spacer 15. The third interlayer insulation layer 15a and the second interlayer insulation layer 16a are continuously patterned to form a capacitor storage node contact 17.
The lower structure of semiconductor substrate composed of the active region 4s, 4d, the bitline contact 14, the capacitor storage node pad 12, the bitline pattern 16, the word line pattern 13 and the capacitor storage node contact 17 etc., is formed by the straight structure.
Referring to FIG. 3, a buffer layer 18 is formed on the semiconductor substrate 11 having the capacitor storage node contact 17. An aperture for connecting the storage node of square type with the capacitor storage node contact 17 is formed through a photolithography and etching process. Metallic material such as tungsten etc. is deposited in the aperture and then a flattening is performed to form a pad contact 19.
Referring to FIG. 4, film material such as silicon nitride layer etc. is deposited to form an etching stop layer 20 on the semiconductor substrate having the pad contact 19. Thereon, a mold oxide layer 21 for a formation of the storage node of capacitor is formed by a thick thickness.
In FIG. 5, an etching mask pattern is formed in the mold oxide layer 21, and an aperture part 22 is formed to expose an upper part of the pad contact 19 connected with the storage node of the capacitor, through an etching process.
In FIG. 6, a chemical vapor deposition(CVD) process is performed on an entire face of the semiconductor substrate having the aperture part 22, to form a conductive layer 23 of polysilicon etc. The conductive layer remained on an upper part of the mold oxide layer is removed through a process such as a flattening etc., to form the capacitor storage node of square type. The capacitor storage node 23a through 23e of square type provides a sectional face of the storage node of the capacitor based on the square type referred to FIG. 1.
In the prior art described above, in order to form a capacitor storage node of square type on a semiconductor substrate based on a conventional straight lower structure, a buffer layer is adapted. Thus, there is a problem of an additional step of forming a pad contact on the buffer layer, the pad contact being for connecting the storage node of square type with a storage node contact of straight structure.